Field of the Invention
The present invention relates generally to integrated circuit (IC) design and, more specifically, to modifying implant regions in an integrated circuit to meet minimum width design rules.
Description of the Related Art
In modern, very large scale integration (VLSI) manufacturing processes, basic logic gates or “cells,” such as AND gates, OR gates, and NOT gates as well as other basic logic gates may be implemented with a variety of speed and power consumption characteristics. The trade-off between the speed and power use of a particular cell is typically accomplished by adjusting the threshold voltage of the transistors that comprise the logic gates, where the threshold voltage is the minimum gate-to-source voltage differential that is needed to create a conducting path between the source and drain terminals of the transistor. Because threshold voltage is a function of dopant ion concentration, threshold voltage for a particular cell may be set by implanting particular elements during manufacturing.
However, in certain manufacturing processes, such as those associated with the 20 nm IC process node, there is a minimum width allowed for implant regions that can be larger than one or more dimension of the implant region associated with a single cell. Consequently, a single cell in an IC that has a different implant property than adjacent cells may not be “manufacturable,” unless relocated within the IC to a location adjacent to a cell or cells having the same implant property. Cell relocation is problematic in the IC design process because relocating a given cell disturbs the already established routing of the IC design. Any changes to routing may adversely impact the overall design schedule of the IC and potentially impact timing and performance of the IC design.
As the foregoing illustrates, there is a need in the art for more effective techniques for achieving minimum width layout requirements for implant regions in an integrated circuit.